Writers: M Norazizi Sham Mohd Sayuti Price: RM 64.00 ISBN: 9786297534848 Publication Year: 2023 Pages: 189 pp. Networks-On-Chip (NoC) is seen as a solution for addressing the limitation of the current bus-based communication in embedded systems. Some of these systems are designed for executing hard real-time services, whose outputs must be delivered within strict timing constraints. Task mapping is a design step that integrates application and hardware. It has a major impact on the timing performance of the services. Existing schedulability analyses are available to evaluate the hard real-time timing performance of task mapping. However, exploring the vast number of task mappings at the early design stage can be challenging due to the influence of other design parameters on the hard real-time performance, the conflicting design objectives, the limitation of the current hard real-time evaluation functions for searching alternative task mappings and the vast evaluation efforts required by the search heuristics. This book explains several design space exploration techniques that address all the issues.

REAL-TIME NETWORK-ON-CHCIP SYSTEM-LEVEL DESIGN SPACE EXPLORATION | Shopee Malaysia